On a Directed Tree Problem Motivated by a Newly Introduced Graph Product

In this paper we introduce and study a directed tree problem motivated by a new graph product that we have recently introduced and analysed in two conference contributions in the context of periodic real-time processes. While the two conference papers were focussing more on the applications, here we mainly deal with the graph theoretical and computational complexity issues. We show that the directed tree problem is NP-complete and present and compare several heuristics for this problem.


Introduction
In this paper we give a detailed discussion of a new graph product that we have recently introduced and analysed in two conference contributions [3,4]. While the two conference papers were focussing more on the applications, here we mainly deal with the graph theoretical and computational complexity issues.
Here we also introduce a new decision problem on directed trees. It is motivated by the applications from the context of periodic real-time processes, and it is based on the new graph product. However, this tree problem can be based on any graph product (or, in fact on any binary operation). Therefore we introduce it now, before going into the technical details of the particular application that motivated it.

A directed tree problem
Let T be a tree, so a connected acyclic (undirected) graph. We orient the tree by replacing each of the edges of T by an arc, in precisely one of the two directions, so we obtain an acyclic weakly connected directed graph, which we call a ditree. A source in a ditree is a vertex with in-degree 0. This is usually referred to as a leaf. A sink in a ditree is a vertex with out-degree 0. We call such a vertex a target of the ditree. We say that a ditree D is a target tree if D has the following properties. Each vertex except for the leaves has in-degree 2; each vertex except for one has out-degree 1; the unique vertex of D (if D has more than one vertex) with in-degree 2 and out-degree 0 is called the target of D.
In our later application, the target v of a target tree D will be interpreted as a special product of two graphs (to be defined in the sequel) that are represented by the two in-neighbours u and w of v in D. If u is a target vertex of D ✁ v, then analogously u can be interpreted as the product of two graphs, etc. On the other hand, each of the ways to compute the product of the graphs G 1 , . . . , G n can be represented as a target tree on n leaves and n ✁ 1 internal vertices (non-leaves). As an example, in Figure 1 we depicted a target tree corresponding to a solution of one of the heuristics called MNSA in the sequel. The leaves at the top represent graphs corresponding to processes, and the internal vertices represent products, e.g., the internal vertex numbered 1 represents the product of G 16 and G 2 , the vertex numbered 8 represents the product of this new graph with G 1 , etc., and the vertex numbered 15 represents the product of the graphs represented by the vertices numbered 14 and 13, respectively. For the MNSA heuristic the order in which the products of the graphs are calculated are given by the numbers of the internal vertices. So the vertex numbered 1 represents the first product, the vertex numbered 2 represents the second product, and so on. In the sequel we will introduce two graph parameters ℓ and M that represent the processing time and memory occupancy of the graph corresponding to (the execution of) a process, and we will define how to compute the value of these parameters for the product of two graphs. As we will see, for the product of two graphs G 1 and G 2 , the ℓ-value is usually lower than the sum of the two ℓ-values of G 1 and G 2 (if the corresponding processes synchronise on certain actions), whereas the M -value of the product is usually larger than the sum of the two M -values. If for the execution of a number of processes on one processor we have a limited memory capacity and a deadline to make, this leads to a decision problem: can we combine the processes in such a way that we can execute them on the processor, meeting the deadline and memory restrictions?
Turning back to the target tree representation, every leaf and every internal vertex of the target tree has an associated ℓ-value and M -value, and corresponds to one process (the leaves) or a subset (product) of more than one process (the internal vertices). Each combination of all the processes into several subsets (products) in which each process occurs in precisely one subset, is represented by a number of leaves (possibly zero) and a number of internal vertices (possibly zero), so that all the chosen vertices of the target tree cover all the leaves. Here a chosen vertex v of the target tree is said to cover all the vertices in all the directed paths from the leaves terminating in v (i.e., v covers all vertices in the (sub)ditree with target vertex v that results after deleting the arc which is directed away from v). We call a set of vertices that covers all the leaves of a target tree D precisely once a leaf cover of D. As an example, the target vertex is a leaf cover of cardinality 1 and the set of leaves is a leaf cover of cardinality n. Every leaf cover also has an associated ℓ-value and M -value (given by the combination of processes it represents, in a way we will explain later). We say that a target tree D on n leaves is feasible if it admits a leaf cover for which the associated ℓ-value and M -value are within the deadline and memory restrictions, so the corresponding combination of processes (corresponding to the sets of products of the graphs G 1 , . . . , G n associated with the n leaves) can be executed correctly on the processor. The above question translates into the following decision problem: given n graphs G 1 , . . . , G n (representing n processes), can we construct a feasible target tree D on n leaves (representing the graphs)? We call this the Synchronised Product Decision Problem. We will show that this decision problem is NP-complete. In fact, for obvious reasons, we will also be interested in a solution, so a target tree together with a leaf cover that provides a YES answer. If the leaf cover contains more than one vertex (so if it is not the target vertex of the target tree), the solution in fact corresponds to a forest of target trees for mutually disjoint subsets of the n leaves.

General introduction
We continue with a general introduction that also contains the motivation for introducing the new graph product.
The software of applications of embedded control systems is often designed using a General Purpose Computing System (GPCS). Such a GPCS often has more processing power and memory available than the embedded control system. The embedded control system is the target system on which the software will run. The hardware of the target system can be very limited with respect to available memory and processing power. If such a target system has to be periodic hard real-time, it has deadlines D for its processes to fulfil the timing requirements, together with memory M to store the data of these processes.
Periodic real-time robotic applications can be designed using formal methods like process algebras [8,9]. While designing, the designer distributes the required behaviour over up to several hundreds of processes. These processes very often synchronise over actions, e.g. to assert that a set of processes will be ready to start executing at the same time. Due to this synchronisation the application suffers from a considerable overhead related to extra context switches.
In [4] we have defined periodic real-time processes as finite deterministic directed acyclic labelled multi-graphs, where these graphs are closely related to state transition systems. The (labelled) arcs in such a graph represent actions in a periodic real-time process. The label represents the name of the action and its duration. As, per action, there is a context switch, the longest path in such a graph is the most time consuming with respect to the context switch and therefore the worst case. We introduced in [4] a Vertex-Removing Synchronised Product (VRSP) to reduce the number of context switches. VRSP is based on the synchronised product of Wöhrle and Thomas [10], which is used in model-checking synchronised products of infinite transition systems.
The VRSP reduces the number of context switches and realises a performance gain for periodic real-time applications. This is achieved by (repetitively) combining two graphs representing two processes that synchronise over some action. This combined graph represents a process that will have only one context switch per synchronising action, where the two processes each have a context switch per synchronising action [4].
Using the VRSP, the set of graphs is transformed into a new set of graphs. For this new set of graphs, either the processes that they represent meet their deadline and fit into the available memory, or there is no set of processes with strong-bisimular behaviour with respect to the original set of processes that will do so.
To be able to compose the set of graphs in a meaningful manner, the VRSP has to be idempotent, commutative and associative. We have defined the notion of consistency for which VRSP is associative. Consistency implies that the processes represented by the graphs are deadlock free in the sense that each process must reach the state where for the process no more actions are specified. In process algebraic terms this is also a deadlock, which we exclude from our definition.
Furthermore we investigate the number of leaf covers in the set of target trees that G can generate under VRSP. This number is given by the Bell number [1].
We introduce a Synchronised Product Decision Problem (SPDP), which describes a solution out of the exponential number of leaf covers in the set of target trees and show that it is NPcomplete.
We have given in [3] heuristics that will calculate in polynomial time a leaf cover under VRSP. Each of the heuristics that we have investigated generates one target tree. These heuristics give no guarantee that the requirements will be fulfilled. In this paper we give another heuristic based on the memory occupancy of the set of graphs. We compare this heuristic with the heuristics given in [3].
The terminology is given in Section 2. From the definition of consistency we derive in Section 2 corollaries that show that the VRSP of two consistent graphs is deadlock free. In Section 3 we show that the VRSP has an identity graph I, that it is commutative, idem-potent and (for consistent components) associative. In Section 4 we give a tree representation of all the combinations of graphs representing a process specification with respect to the summation over the VRSPs. In Section 5 we define the Synchronised Product Decision Problem (SPDP) for the tree representation of Section 4 and show that it is NP-complete. A heuristic based on the memory occupancy is given in Section 6. We finish with the conclusions in Section 7. The pseudo-code of the heuristics is given in the Appendix.

Terminology
We use Bondy and Murty [2], Hammack et al. [5], Hell and Nešetřil [6] and Milner [9] for terminology and notation on graphs and processes not defined here and consider finite labelled weighted deterministic directed acyclic multi-graphs only. In order to make this paper self contained as far as the new terminology is concerned, we repeat the notions as they were introduced in [4] for convenience. So, if we use G to denote a graph, we mean a labelled weighted deterministic directed acyclic multi-graph. Thus G consists of a set of vertices V , a multi-set of arcs A, and a surjective mapping λ : A Ñ L, where L is a set of label pairs. G is also denoted as G ✏ ♣V, A, Lq.
An arc a A which is directed from a vertex v V (the tail) to a vertex w V (the head) will usually be denoted as a ✏ vw. For each arc a A, λ♣aq L consists of a pair ♣l♣aq, t♣aqq, where l♣aq is a string representing an action and t♣aq is a positive real number representing the worst-case execution time of the action represented by l♣aq. If an arc has multiplicity k → 1, then all copies have different label pairs, otherwise we could replace two copies of an arc with identical label pairs by one arc, because they represent exactly the same action at the same stage of the process. If two arcs a, b A have label pairs λ♣aq ✏ ♣l♣aq, t♣aqq and λ♣bq ✏ ♣l♣bq, t♣bqq such that l♣aq ✏ l♣bq, then this implies that t♣aq ✏ t♣bq; this follows since l♣aq ✏ l♣bq means that the arcs a and b represent the same action at different stages of a process.
The identity graph consists of one vertex and no arcs (and therefore no label pairs) and is denoted as I, so I ✏ ♣ti✉, ❍, ❍q.
The empty graph consists of no vertices and no arcs and is denoted as This is equivalent to determinism in the set of processes that represents the graph G.
We consider finite directed acyclic graphs, G, only. In general, such a graph consists of several components, where each component, G i , is weakly connected (i.e. all vertices are connected by sequences of arcs, ignoring arc directions) and corresponds to one sequential process. For such components, ℓ♣G i q is defined as the maximum length taken over all directed paths in G i . For the whole graph, which corresponds to a parallel set of sequential processes that must each run to If G represents one process, then m♣Gq represents the amount of memory needed to store the related data-structures. We consider finite graphs only, therefore m♣Gq is finite. Usually G consists of several components, where each component G i of G corresponds to one process. Then m♣G i q represents the amount of memory needed to store the related data-structures for G i .
from the source to the sink of the component G i .
For each G i we define S i 0 to denote the set of vertices with in-degree 0 in G i , S i 1 the set of vertices with in-degree 0 in the graph obtained from G i by deleting the vertices of S i 0 and all arcs with tails in S i 0 , and so on, until the final set S i t i contains the remaining vertices with in-degree 0 and there are no arcs in the remaining component. As in the acyclic ordering, this ordering implies that arcs of G i can only exist from a vertex in S i j 1 to a vertex in S i in the set S i j in the above ordering, we also say that v is at level j in G i .
The union of two vertex-disjoint graphs G i and G j is the graph consisting of the union of the vertex sets of G i and G j together with all the multi-arcs and label pairs defined by G i and G j .

Graph Products
The Cartesian product G i ✂ G j of G i and G j is defined as the multi-graph on vertex set V i,j ✏ V i ✂ V j (the Cartesian product of the vertex sets of G i and G j ) with two types of arcs. Arcs of type , so arcs of type 1 and 2 correspond to arcs of G i and G j , respectively.

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On a directed tree problem motivated by a newly introduced graph product | Antoon H. Boode et al. This definition of the Cartesian product is an extension of the Cartesian product in [5]: In the sequel the Cartesian product G i ✂ G j is denoted as G i •G j ; a notation we adopted from [5].
The synchronised product of G i and G j is constructed in two stages.
Firstly, the intermediate stage, denoted as G i ❜ G j of G i and G j , is defined as the graph on vertex set V i,j ✏ V i ✂ V j with two types of arcs: -Arcs of type 1 are between pairs ♣ These arcs of G i ❜ G j are called asynchronous arcs, and the set of these arcs is denoted as A a i,j . Thus, These arcs of G i ❜ G j are called synchronous arcs, and the set of these arcs is denoted as The intermediate stage of the synchronised product is similar to the synchronised product defined by Wöhrle and Thomas [10]. Secondly, all vertices at level 0 in the intermediate stage that are at level → 0 in G i •G j are removed, together with all the arcs that have one of these vertices as a tail. This is then repeated in the newly obtained graph, and so on, until there are no more vertices at level 0 in the current graph that are at level → 0 in G i •G j . The resulting graph is called the Vertex Removing Synchronised Product (VRSP) of G i and G j , denoted as G i ♥ G j . VRSP is also called the synchronised product if no confusion can arise. For k ➙ 3, the VRSP The summation over products of components is denoted as G Remark 2.1. The asynchronous arcs are created in a similar fashion as the arcs in the Cartesian product.
Remark 2.2. A pair of synchronous arcs from G 1 and G 2 are replaced by one arc in G 1 ❜ G 2 .

Graph-morphisms
which is denoted by f ✝ . Remark 2.3. Label pairs have been added to the definition of a weak-homomorphism as defined by Hammack et al. [5].
Components G i and G j are consistent if and only if the following two requirements apply: 1. There exist weak-homomorphisms ρ i and ρ j such that ρ i : Corollary 2.1. Let components G 1 and G 2 be consistent. For every full path of G 1 ♥ G 2 there exists a full path of G 1 (possibly after skipping arcs of the path in G 1 ♥ G 2 that then belong to G 2 ) and there exists a full path of G 2 (possibly after skipping arcs of the path in G 1 ♥ G 2 that then belong to G 1 ; the skipped arcs are asynchronous arcs.) Proof. Because G 1 and G 2 are consistent there exist weak-homomorphisms ρ 1 and ρ 2 such that These weak-homomorphisms ρ 1 and ρ 2 have the property that for all full paths w 1 w 2 . . . w n in G 1 ♥ G 2 and for every arc w i w i 1 there is an arc u j u j 1 in A 1 with λ♣w i w i 1 q ✏ λ♣u j u j 1 q or there is an arc v k v k 1 in A 2 with λ♣w i w i 1 q ✏ λ♣v k v k 1 q. Such an arc may exist for both weak-homomorphisms ρ 1 and ρ 2 , so for ρ 1 ♣w i w i 1 q ✏ u j u j 1 and If for an arc w i w i 1 with λ♣w i w i 1 q ✏ a, ρ 1 maps w i and w i 1 to u j then u j u j 1 with λ♣u j u j 1 q ✏ a is not in A 1 . By repetition, skipping arcs that map by ρ 2 to A 2 , there must be a w j w j 1 with ρ 1 ♣w j q ✏ u j , ρ 1 ♣w j 1 q ✏ u j 1 and u j u j 1 A 1 and λ♣w j w j 1 q ✏ λ♣u j u j 1 q, because otherwise u j V and there is a vertex v x G 2 ♣V q for which ♣u j , v x q G 1 ♥G 2 ♣V q. Analogously, by repetition, skipping arcs that map by ρ 2 to A 2 , there must be a w j✁1 w j with ρ 1 ♣w j✁1 q ✏ u j✁1 , ρ 1 ♣w j q ✏ u j and u j✁1 u j A 1 and λ♣w j✁1 w j q ✏ λ♣u j✁1 u j q, because otherwise u j V ✁ and there is a vertex v Vice versa for ρ 2 and arcs that are not in G 2 .
From this it follows that all paths w 2 w 3 . . . w n✁1 by ρ 1 (ρ 2 ) are mapped to some path u 2 u 3 . . . u k (v 2 v 3 . . . v l ). But ρ 1 (ρ 2 ) maps w 1 to u 1 (v 1 ) and w n to u k 1 (v l 1 ) and therefore u 1 u 2 . . . u k 1 Corollary 2.2. Let components G 1 and G 2 be consistent. For every full path in G 1 ♣G 2 q there exists a full path in G 1 ♥ G 2 (posibly after skipping arcs of the path in G 1 ♥ G 2 that then belong to G 2 ♣G 1 q).
together with Corollary 2.1, for every full path in G 1 (G 2 ) there exists a full path in G 1 ♥ G 2 . Corollary 2.3. If components G 1 and G 2 are consistent, then G 1 ♥ G 2 is deadlock free.
Proof. Follows directly from Corollary 2.1 and Corollary 2.2.
Both requirements of consistency are necessary to exclude a deadlock in the processes represented by the components. The first requirement of consistency ensures that all paths in the components are (upto isomorphism) also in the VRSP of these components. An example that violates this requirement is given in Figure 2  An example of consistent components is given in Figure 4, where we have the components Then we have the weak-homomorphisms Remark 2.4. ρ 1 is also a homomorphism.

Basic Properties of the VRSP
We start with propositions on identity, the empty graph, commutativity and idem-potency, which are easy to prove. We use deterministic graphs, because of the required idem-potency of components. An example of a non-deterministic graph is given in Figure 5. Figure 5. Non-deterministic and not idem-potent component.
We state the six propositions without proof. Let G be a finite directed acyclic labelled multi-graph.
Let G 1 , G 2 and G 3 be deterministic finite directed acyclic labelled multi-graphs, in which all components are pairwise consistent in Proposition 3.4 through 3.6. Note that G 1 , G 2 and G 3 are pairwise vertex disjoint. This follows directly from G 1 , G 2 and G 3 being components.
Proposition 3.4. The synchronised product of G 1 and G 2 is commutative up to isomorphism. So Proposition 3.5. The synchronised product of G 1 and G 1 , Note that an arc u i v i A♣G 1 q and an arc u j v j A♣G 1 q, with λ♣u i v i q ✏ λ♣u j v j q, i ✘ j, ♣u i , u j q has level → 0 in G 1 •G 1 and level ✏ 0 in G 1 ❜G 1 (possibly after removing vertices with the same condition) and therefore ♣u i , u j q (and consequently ♣u i , u j q♣v i , v j q) will be removed. Proposition 3.6. The addition over G 1 and G 1 , The synchronised product does not distribute over the addition up to isomorphism. So G 1 ♥ ♣G 2 G 3 q ✢ ♣G 1 ♥ G 2 q ♣G 1 ♥ G 3 q. This follows from the example shown in Figure 6. The set of label pairs used by VRSP are restricted to the label pairs in the components that are multiplied.
Then the synchronised product is associative up to isomorphism. In particular, given components Proof. Assume there is a full path x 1 . . . x m in G 1 ♥ ♣G 2 ♥ G 3 q and any full path t 1 .
Because G 1 and G 2 ♥ G 3 are consistent, there exist weak-homomorphisms ρ 1 and ρ 2 with a full path u 1 . . . u i in G 1 , where ρ 1 ♣x 1 . . . x m q ✏ u 1 . . . u i and a full path y 1 . . . y l in G 2 ♥ G 3 , where ρ 2 ♣x 1 . . . x m q ✏ y 1 . . . y l . Then there exist weak-homomorphisms ρ 3 and ρ 4 with a full path v 1 . . . v j in G 2 , where ρ 3 ♣y 1 . . . y l q ✏ v 1 . . . v j and a full path w 1 . . . w k in G 3 , where ρ 4 ♣y 1 . . . y l q ✏ w 1 . . . w k . But, due to Corollary 2.2, because u 1 . . . u i is a full path in G 1 and v 1 . . . v j is a full path in G 2 , there is a full path z 1 . . . z n in G 1 ♥ G 2 . For these two full paths w 1 . . . z k and z 1 . . . z n there is a full path t 1 . . . t o in ♣G 1 ♥ G 2 q ♥ G 3 , contradicting our assumption.
Thus for every full path in G 1 ♥♣G 2 ♥G 3 q there exists a full path in ♣G 1 ♥G 2 q♥G 3 . Analogously for every full path in ♣G 1 ♥ G 2 q ♥ G 3 there exists a full path in Figure 7 shows the weak-homomorphisms ρ i from a set of full paths of the VRSP of two components to these components. Associativity is necessary to calculate the number of possible leaf covers of a target tree D by the Bell number, given in Section 4.

Feasibility of a Target Tree
Let D be a target tree. Recall that the leaves of D represent processes as specified by the designer of the periodic real-time application. A leaf cover of D is a solution if it represents a set of (combined) processes that meet their deadlines and fit in the available memory. The www.ejgta.org On a directed tree problem motivated by a newly introduced graph product | Antoon H. Boode et al. cardinality of the set of leaf covers of all target trees over n leaves is given by the Bell number , Because for two isomorphic target trees the order in which VRSP is executed over components can be different, the synchronised product of the components of the graph G has to be associative . For this reason the components in the graph G have to be consistent. Moreover each product of components has to be consistent with the other remaining components. Figure 8 gives an example where G 1 , G 2 and G 3 are pairwise consistent. But G 1 ♥ G 2 and G 3 are not pairwise consistent. Therefore a heuristic has to check whether the components are still consistent after every multiplication by VRSP.

Synchronised Product Decision Problem
The cardinality of the set of leaf covers of all target trees over n leaves has an exponential distribution. We show that a leaf cover of a target tree D can be checked in polynomial time.
Definition 1. A monoid ♣G, ♥ q is an algebraic structure which is closed under the associative operator ♥ and has the identity element I, where G is generated by G under ♥.

Definition 2. Synchronised Product Decision Problem (SPDP)
Let ♣G, ♥ q be a monoid, together with a memory budget M and a deadline D. Can a feasible target tree D on V ♣Gq be constructed?
Note that G ➦ ♥ is represented by a leaf cover of D. SPDP is in NP if there exists some oracle that points out a solution and there exists an algorithm that can check the solution in polynomial time. To formalise this, we need the following definitions, let: • A i ♣aq be the set of arcs ta i ⑤a i A i ) λ♣a i q ✏ a✉ the calculation can stop, as further multiplications will not lead to a solution. In this case, G ➦ ♥ is not a solution that full-fills the requirements for the deadline and memory occupancy.
Remark 5.1. This is only true because the components (and the products of the components) are consistent. Furthermore, the calculation is not performed in the target system but in a general purpose computing system, so the available memory may be significantly greater than the memory available in the target system.
Having calculated the synchronised product G ➦ ♥ and performing a breadth first search for each component, we obtain the length of G ➦ ♥ , ℓ♣G ➦ ♥ q. Therefore we have in polynomial time an answer whether the oracle's solution is valid. Because G ➦ ♥ is represented by a leaf cover in the target tree D, a valid solution implies that D is feasible.
For these reasons SPDP is in NP.
Leung [7] defines the 0/1-Knapsack Decision Problem (KDP). Given a set U ✏ tu 1 , u 2 , ☎ ☎ ☎ , u n ✉ with each item u j having a size s j and a value v j , a knapsack with size K, and a bound B. Is there Let v j be a vertex in a leaf cover LC with cardinality k of D, where D is a target tree generated by G.
LC is a solution for SPDP.
Conversely, if LC is a solution for SPDP, then ℓ♣LCq ↕ D and m♣LCq ↕ M ✏ K, therefore  [3] together with the algorithm introduced in this paper, Minimal Memory Occupancy (MMO), given in the Appendix, Algorithm 2.
The level of the tail of a synchronising arc determines whether LAI or MMO will perform better. For two components where these levels are low in one component and high in the other component, MMO will perform better because the VRSP over these two components will be (almost) optimal with respect to memory occupancy. Whereas LAI may choose two components with a larger alphabetical intersection that have the levels for tails of the synchronising arcs that are relatively on the same level. But with respect to the length of the product of the components this can be the opposite.
In Figure 9 we give for the Production Cell case study in [3] the results for the four algorithms, MNSA, LAI, MSA and MMO. Note the logarithmic scale in the y-abyss. Due to the specification of the processes where each process synchronises over at least one action with all other processes, MMO performs best up till the last multiplication. To achieve a length of 37 LAI has the best (is minimal) memory occupancy.
The algorithms replace two components by their product until all components are multiplied. So from a leaf cover with cardinality n to a leaf cover with cardinality 1.

Conclusions
A set of processes that does not meet its deadline or does not fit in the available memory can, under certain conditions, be transformed into a set of processes that will fulfil both requirements. For this transformation we use our Vertex Removing Synchronised Product (VRSP) on consistent finite labelled weighted deterministic directed acyclic multi-components.
We have given a definition for consistency such that consistent components are deadlock free. This is essential for the processes represented by these components, because otherwise in the target system deadlines will be missed. Missing a deadline leads to a catastrophe in hard realtime systems.
We have given conditions and proof for VRSP to be commutative, associative and idem-potent. This is necessary because otherwise components may not be pairwise consistent.
We have introduced a directed tree problem motivated by VRSP in the context of periodic hard real-time processes. The number of target trees is exponential with respect to the number of components, representing the original set of processes and is given by the Bell number. We have dealt with the graph theoretical and computational complexity issues. We have shown that the directed tree problem is NP-complete and we have presented and compared several heuristics for this problem.
Because SPDP is NP-complete, in practice heuristics have to be used (like MMO and the ones we proposed in [3]) to calculate a set of components which represent processes that will not be tardy and fit in the available memory. We have introduced a new heuristic based on memory occupancy that shows for our case study that its performance is in most cases better than the heuristics given in [3].
In our case the new set of processes is calculated off-line during the design process and forms no burden on the target system, in our case an active real-time system.
Because the components have to be consistent, to compose the original set of components, the designer is limited in his description of the system. In our view this is not a problem, because, if the set of graphs would be not consistent, it contains graphs that represent processes that form a deadlock. This is a situation that has to be avoided.